View LC87F7J32A_7939909.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

o1707hkim 20071009-s00002 no.a0886-1/29 ver1.00 LC87F7J32A overview the sanyo LC87F7J32A is an 8-bit microcomputer that, ce ntered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single ch ip a number of hardware features su ch as 32k-byte flash rom (onboard programmable), 1024-byte ram, an on-chip debugger, a lcd controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time- of-day clock, a day and time counter, a synchronous sio interface (with automatic block transmission/reception capabilities), an asynchronous/s ynchronous sio interface, a uart interface (full duplex), two 12-bit pwm channels, a 12-bit/8-bit 10-channel ad converter, remote control rece ive function, a high-speed clock counter, a system clock frequency divider, an internal reset and a 25-source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 3.0 to 5.5v,of voltage souce ? block-erasable in 128-byte units ? 32768 8 bits ? ram ? 1024 9 bits ? minimum bus cycle time ? 83.3ns (12mhz) v dd =3.0 to 5.5v ? 125ns (8mhz) v dd =2.5 to 5.5v ? 250ns (4mhz) v dd =2.2 to 5.5v note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ? 250ns (12mhz) v dd =3.0 to 5.5v ? 375ns (8mhz) v dd =2.5 to 5.5v ? 750ns (4mhz) v dd =2.2 to 5.5v ordering number : ena0886 cmos ic from 32k byte, ram 1024 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd.
LC87F7J32A no.a0886-2/29 ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units 15 (p1n, p30 to p31, p70 to p73, xt2) ports whose i/o direction can be designated in 4 bit units 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? normal withstand voltage input port 1 (xt1) ? lcd ports segment output 24 (s00 to s23) common output 4 (com0 to com3) bias terminals for lcd driver 3 (v1 to v3) other functions input/output ports 24 (pan, pbn, pcn,) input ports 7 (pln) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pin 1 ( res ) ? power pins 6 (v ss 1 to v ss 3, v dd 1 to v dd 3) ? lcd controller 1) seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) 2) segment output and common output can be switched to general-purpose input/output ports ? timers ? timer 0: 16-bit timer/counter with two capture registers. mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 8: 16-bit timer mode 0: 8-bit timer with an 8-bit prescaler 2 channels (with toggle output) mode 1: 16-bit timer with an 8-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? day and time counter 1) using with a base timer,it can be used as 65000 day + minute + second counter. ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real-time.
LC87F7J32A no.a0886-3/29 ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8-data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8-data bits, stop detect) ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? ad converter: 12-bits/8-bits 12 channels ? 12 bits/8 bits ad converter resolution selectable ? pwm: multi frequency 12-bit pwm 2 channels ? infrared remote control receiver circuit 1) noise reduction function (noise filter time constant: approx. 120 s, when the 32.768khz crystal oscilla tor is selected as the reference voltage source.) 2) supports data encoding systems such as ppm (pulse position modulation) and manchester encoding 3) x ? tal hold mode release function ? watchdog timer ? external rc watchdog timer ? basetimer watchdog timer ? interrupt and reset signals selectable ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) able to output oscillation clock of sub clock.
LC87F7J32A no.a0886-4/29 ? interrupts ? 25 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interr upts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/remote control receiver 4 0001bh h or l int3/int5/bt0/bt1 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart1 transmit 9 00043h h or l adc//t6/t7/pwm4/pwm5 10 0004bh h or l port 0/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) 1) shows a list of interrupt source flags that cau sed a branching to a particular vector address (shown in the diagram above). ? subroutine stack levels: 512 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf ? crystal oscillation circuit: for low-spee d system clock, with internal rf ? frequency variable rc oscillation circuit (internal): for system clock 1) adjustable in 4% (typ) step from a selected center frequency. 2) measures oscillation clock using a input signal from xt1 as a reference. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? internal reset function ? power-on-reset (por) function 1) por resets the system when the power supply voltage is applied. 2) por release level is selectable from 4 levels (2.07v, 2.37v, 2.87v, 4.35v) by option. ? low voltage detection reset (lvd) function 1) lvd used with por resets the system when the supply voltage is applied and when it is lowered. 2) lvd function is selectable from enable/disable and the reset level is selectable from 3 levels (2.31v, 2.81v, 4.28v) by option.
LC87F7J32A no.a0886-5/29 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (some parts of the serial transfer function stops operation) 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, x?tal, and frequency variable rc oscillators automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2, int4, and int5, pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer and the remote control circuit. 1) the cf, rc, and frequency variable rc oscillators automatically stop operation 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4,and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an interrupt source established in the infrared remote control receiver circuit ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? package form ? qip64e(14 14): lead-free type ? tqfp64j(10 10): lead-free type ? development tools ? on-chip debugger: tcb87-typeb + LC87F7J32A ? flash rom programming board package programming boards qip64e(14 14) w87f50256q tqfp64j(10 10) w87f57256sq ? flash rom programmer maker model supported version (note) device single af9708/af9709/ af9709b after 0x.xx af9723 (main body) after 0x.xx flash support group, inc. (formerly ando electric co., ltd.) gang af9833 (unit) after 0x.xx sanyo skk (sanyo fws) after x.xxa LC87F7J32A note: please check the latest version. ? same package and pin assignment as mask rom version. 1) lc877j00 series options can be set by using flash rom data. thus the board used for mass production can be used for debugging and evaluation without modifications. 2) if the program for the mask rom version is us ed, the usable rom/ram capacity is the same as the mask rom version.
LC87F7J32A no.a0886-6/29 package dimensions unit : mm (typ) 3159a package dimensions unit : mm (typ) 3310 sanyo : qip64e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64 sanyo : tqfp64j(10x10) 12.0 12.0 0.1 1.2 max 0.5 0.18 10.0 10.0 0.125 0.5 (1.25) (1.0) 116 17 32 33 48 49 64
LC87F7J32A no.a0886-7/29 pin assignment sanyo: qip64e(14 14) ?lead-free type? sanyo: tqfp64j(10 14) ?lead-free type? com3/pl3 com2/pl2 com1/pl1 com0/pl0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 v dd 3 v ss 3 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1/urx1 s0/pa0/utx1 p07/t7o p06/t6o p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 v1/pl4/an0/dbgp0 v2/pl5/an1/dbgp1 v3/pl6/an2/dbgp2 p10/so0 p11/si0/sb0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 LC87F7J32A 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/ t1pwml p17/t1pwmh/buz p30/int4/t1in/t0lcp/pwm4 p31/int5/t1in/t0hcp/pwm5 v dd 2 v ss 2 p00/an3 p01/an4 p02/an5 p03/an6 p04/an7 p05/cko 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 top view
LC87F7J32A no.a0886-8/29 pin no. name pin no. name 1 p12/sck0 33 s14/pb6 2 p13/so1 34 s15/pb7 3 p14/si1/sb1 35 v ss 3 4 p15/sck1 36 v dd 3 5 p16/t1pwml 37 s16/pc0 6 p17/t1pwmh/buz 38 s17/pc1 7 p30/int4/t1in/t0lcp1/pwm4 39 s18/pc2 8 p31/int5/t1in/t0hcp1/pwm5 40 s19/pc3 9 v dd 2 41 s20/pc4 10 v ss 2 42 s21/pc5 11 p00/an3 43 s22/pc6 12 p01/an4 44 s23/pc7 13 p02/an5 45 com0/pl0 14 p03/an6 46 com1/pl1 15 p04/an7 47 com2/pl2 16 p05/cko 48 com3/pl3 17 p06/t6o 49 p70/int0/t0lcp/an8 18 p07/t7o 50 p71/int1/t0hcp/an9 19 s0/pa0/utx1 51 p72/int2/t0in 20 s1/pa1/urx1 52 p73/int3/t0in 21 s2/pa2 53 res 22 s3/pa3 54 xt1/an10 23 s4/pa4 55 xt2/an11 24 s5/pa5 56 v ss 1 25 s6/pa6 57 cf1 26 s7/pa7 58 cf2 27 s8/pb0 59 v dd 1 28 s9/pb1 60 v1/pl4/an0/dbgp0 29 s10/pb2 61 v2/pl5/an1/dbgp1 30 s11/pb3 62 v3/pl6/an2/dbgp2 31 s12/pb4 63 p10/so0 32 s13/pb5 64 p11/si0/sb0
LC87F7J32A no.a0886-9/29 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 0 port 1 sio0 sio1 timer 0 (high speed clock counter) timer 1 timer 6 timer 7 adc port 3 port 7 int0 to 5 noise rejection filter acc b register c register psw rar ram stack pointer watchdog timer alu lcd controller pwm4 base timer uart1 on-chip debugger clock generator cf rc vmrc x?tal pwm5 timer 4 timer 5 remote control receiver circuit day and time counter reset circuit (lvd/por) wtd reset control res
LC87F7J32A no.a0886-10/29 pin description pin name i/o description option v ss 1 v ss 2 v ss 3 - - power supply pin no v dd 1 v dd 2 v dd 3 - + power supply pin no port0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? input for hold release ? input for port 0 interrupt ? shared pins p00 to p04: ad converter input (an3 to an7) p05: clock output (system clock/can selected from sub clock) p06: timer 6 toggle output p07: timer 7 toggle output yes port1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes port3 p30 to p31 i/o ? 2-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p30: int4 input/hold release input/timer 1 event input/timer 0l capture input/pwm4 p31: int5 input/hold release input/timer 1 event input/timer 0l capture input/pwm5 ? interrupt acknowledge type rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable yes port7 p70 to p73 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p70: int0 input/hold release input/timer 0l capture input/watchdog timer output p71: int1 input/hold release i nput/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/timer 0 event input/timer 0h capture input/ remote control receiver input ad converter input ports: an8 (p70), an9 (p71) ? interrupt acknowledge type rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable no continued on next page.
LC87F7J32A no.a0886-11/29 continued from preceding page. pin name i/o description option s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pb) no s16/pc0 to s23/pc7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pc) no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general-purpose input port (pl) no v1/pl4 to v3/pl7 i/o ? lcd output bias power supply ? can be used as general-purpose input port (pl) ? shared pins ad converter input ports: an0 (v1) to an2 (v3) on-chip debugger pins: dbgp0 (v1) to dbgp2 (v3) no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port ad converter input port: an10 must be connected to v dd 1 if not to be used. no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
LC87F7J32A no.a0886-12/29 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note) p00 to p07 1 bit 2 n-channel open drain no 1 cmos programmable p10 to p17 1 bit 2 n-channel open drain programmable 1 cmos programmable p30 to p31 1 bit 2 n-channel open drain programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable s0/pa0 to s23/pc7 - no cmos programmable com0/pl0 to com3/pl3 - no input only no v1/pl4 to v3/pl6 - no input only no xt1 - no input for 32.768 khz crystal oscillator (input only) no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no note1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). *1 connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. *2 the internal memory is sustained by v dd 1. if none of v dd 2 and v dd 3 are backed up, the high level output at the ports are unstable in the hold backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. make sure that the port outputs are held at the low level in the hold backup mode. power suppl y lsi v dd 1 for backup v dd 2 v dd 3 v ss 3 v ss 2 v ss 1
LC87F7J32A no.a0886-13/29 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 v dd 1=v dd 2=v dd 3 -0.3 v dd input voltage v i (1) port l xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) port 0, 1, 3, 7 port a, b, c xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1 ports a, b, c ? cmos output selected ? current at each pin -10 ioph(2) port 3 ? cmos output selected ? current at each pin -20 peak output current ioph(3) port 71 to 73 current at each pin -5 iomh(1) ports 0, 1 ports a, b, c ? cmos output selected ? current at each pin -7.5 iomh(2) port 3 ? cmos output selected ? current at each pin -15 mean output current (note 1-1) iomh(3) ports 71 to 73 current at each pin -3 ioah(1) ports 71 to 73 total of all pins -5 ioah(2) port 1 total of all pins -20 ioah(3) ports 1, 71 to 73 total of all pins -20 ioah(4) port 3 total of all pins -25 ioah(5) port 0 total of all pins -20 ioah(6) ports 0, 3 total of all pins -40 ioah(7) ports a, b total of all pins -25 ioah(8) port c total of all pins -20 high level output current total output current ioah(9) ports a, b, c total of all pins -10 iopl(1) ports 0, 1 ports a, b, c current at each pin 20 iopl(2) port 3 current at each pin 30 peak output current iopl(3) ports 7, xt2 current at each pin 10 ioml(1) ports 0, 1 ports a, b, c current at each pin 15 ioml(2) port 3 current at each pin 20 mean output current (note 1-1) ioml(3) ports 7, xt2 current at each pin 7.5 ioal(1) ports 7, xt2 total of all pins 15 ioal(2) ports 1 total of all pins 40 ioal(3) ports 1, 7, xt2 total of all pins 50 ioal(4) port 3 total of all pins 45 ioal(5) port 0 total of all pins 40 ioal(6) ports 0, 3 total of all pins 80 ioal(7) ports a, b total of all pins 45 ioal(8) port c total of all pins 40 low level output current total output current ioal(9) ports a, b, c total of all pins 80 ma qip64e(14 14) ta=-40 to +85 c 298 power dissipation pd max tqfp64j(10 10) ta=-40 to +85 c mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms.
LC87F7J32A no.a0886-14/29 allowable operating condtions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0-237 s tcyc 200 s 3.0 5.5 0-356 s tcyc 200 s 2.5 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0-712 s tcyc 200 s 2.2 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode 2.0 5.5 v ih (1) ? ports 0, 3 ? ports a, b, c ? port l output disabled 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ? port 1 ? ports 71 to 73 ? port 70 port input/ interrupt side ? output disabled ? when int1vtsl=0 (p71only) 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) port 71 interrupt side ? output disabled ? when int1vtsl=1 2.2 to 5.5 0.85v dd v dd v ih (4) port 70 watchdog timer side output disabled 2.2 to 5.5 0.9v dd v dd high level input voltage v ih (5) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (1) ? ports 0, 3 ? ports a, b, c ? port l output disabled 2.2 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.1v dd +0.4 vil( 2) ? port 1 ? ports 71 to 73 ? port 70 port input/interrupt side ? output disabled ? when int1vtsl=0 (p71 only) 2.2 to 4.0 v ss 0.2v dd v il (3) port 71 interrupt side ? output disabled ? when int1vtsl=1 2.2 to 5.5 v ss 0.45v dd v il (4) port 70 watchdog timer side 2.2 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (5) xt1, xt2, cf1, res 2.2 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.237 200 2.5 to 5.5 0.356 200 instruction cycle time (note 2-2) tcyc 2.2 to 5.5 0.712 200 s 3.0 to 5.5 0.1 12 2.5 to 5.5 0.1 8 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=505% 2.2 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 2.2 to 5.5 0.2 8 mhz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. continued on next page.
LC87F7J32A no.a0886-15/29 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit fmcf(1) cf1, cf2 ? 12mhz ceramic oscillation ? see figure 1. 3.0 to 5.5 12 fmcf(2) cf1, cf2 ? 8mhz ceramic oscillation ? see figure 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 ? 4mhz ceramic oscillation ? see figure 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmvmrc(1) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=0 2.2 to 5.5 10 fmvmrc(2) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=1 2.2 to 5.5 4 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 ? 32.768khz crystal oscillation ? see figure 2. 2.2 to 5.5 32.768 khz opvmrc(1) when vmsl4m=0 2.2 to 5.5 8 10 12 frequency variable rc oscillation usable range opvmrc(2) when vmsl4m=1 2.2 to 5.5 3.5 4 4.5 mhz vmadj(1) each step of vmrajn (wide range) 2.2 to 5.5 8 24 64 frequency variable rc oscillation adjustment range vmadj(2) each step of vmfajn (small range) 2.2 to 5.5 1 4 8 % note 2-3: see tables 1 and 2 for the oscillation constants. electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 3, 7 ? ports a, b, c ? port l ? output disabled ? pull-up resistor off ? v in =v dd (including output tr's off leakage current) 2.2 to 5.5 1 i ih (2) res v in =v dd 2.2 to 5.5 1 i ih (3) xt1, xt2 ? for input port specification ? v in =v dd 2.2 to 5.5 1 high level input current i ih (4) cf1 v in =v dd 2.2 to 5.5 15 i il (1) ? ports 0, 1, 3, 7 ? ports a, b, c ? port l ? output disabled ? pull-up resistor off ? v in =v ss (including output tr's off leakage current) 2.2 to 5.5 -1 i il (2) res v in =v ss 2.2 to 5.5 -1 i il (3) xt1, xt2 ? for input port specification ? v in =v ss 2.2 to 5.5 -1 low level input current iil(4) cf1 v in =v ss 2.2 to 5.5 -15 a continued on next page.
LC87F7J32A no.a0886-16/29 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (6) ports 30, 31 i oh =-1ma 2.2 to 5-5 v dd -0.4 v oh (7) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (8) ports 71 to 73 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (9) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (10) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (11) ports a, b, c i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1 ports 3 (pwm function output mode) i ol =1ma 2.2 to 5.5 0.4 v ol (4) i ol =30ma 4.5 to 5.5 1.5 v ol (5) i ol =5ma 3.0 to 5.5 0.4 v ol (6) ports 3 (port function output mode) i ol =2.5ma 2.2 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) ? port 7 ? xt2 i ol =1ma 2.2 to 5.5 0.4 v ol (9) i oh =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (10) ports a, b, c i ol =1ma 2.2 to 5.5 0.4 vodls s0 to s23 ? i o =0ma ? vlcd, 2/3vlcd, 1/3vlcd level output ? see fig. 8. 2.2 to 5.5 0 0.2 lcd output voltage deviation vodlc com0 to com3 ? i o =0ma ? vlcd, 2/3vlcd, 1/2vlcd, 1/3vlcd level output ? see fig. 8. 2.2 to 5.5 0 0.2 v rlcd(1) resistance per one bias resister see fig. 8. 2.2 to 5.5 80 lcd bias resistor rlcd(2) resistance per one bias resister 1/2r mode see fig. 8. 2.2 to 5.5 40 rpu(1) 4.5 to 5.5 15 35 80 resistance of pull-up mos tr. rpu(2) ports 0, 1, 3, 7 ports a, b, c v oh =0-9v dd 2.2 to 5.5 18 50 150 k hysteresis voltage vhys(1) ports 1, 7 res 2.2 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.2 to 5.5 10 pf
LC87F7J32A no.a0886-17/29 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.2 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.2 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.2 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 tddo(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.2 to 5.5 ( 1/3)tcyc +0.05 input clock tddo(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.2 to 5.5 1tcyc +0.05 serial output output clock output delay time tddo(3) so0(p10), sb0(p11) (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.15 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC87F7J32A no.a0886-18/29 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig.6. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 2.2 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tddo(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p30), int5(p31) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tcyc tpih(5) tpil(5) rmin(p73) recognized by the infrared remote controller receiver circuit as a signal. 2.2 to 5.5 4 rmck (note5-1) high/low level pulse width tpil(6) res resetting is enabled. 2.2 to 5.5 200 s note 5-1: represents the period of the reference clock (1tcyc to 128tcyc or the source frequency of the subclock ) for the infrared remote controller receiver circuit
LC87F7J32A no.a0886-19/29 ad converter characteristics at v ss 1 = v ss 2 = v ss 3 =0v <12bits ad converter mode at ta =-40 to +85 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.0 to 5.5 32 115 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(v1) to an2(v3), an3(p00) to an7(p04), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 3.0 to 5.5 -1 a <8bits ad converter mode at ta =-40 to +85 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.0 to 5.5 20 90 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(v1) to an2(v3), an3(p00) to an7(p04), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas: 12bits ad converter mode: tcad(conversion time)=((52/(division ratio)) + 2) (1/3) tcyc 8bits ad converter mode: tcad(conversion time)=((32/(division ratio)) + 2) (1/3) tcyc ad conversion time (tcad) external oscillation (fmcf) operating supply voltage range (vdd) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) 12bit ad 8bit ad 4.0v to 5.5v 1/1 250ns 1/8 34.8 s 21.5 s cf-12mhz 3.0v to 5.5v 1/1 250ns 1/16 69.5 s 42.8 s 4.0v to 5.5v 1/1 375ns 1/8 52.2 s 32.3 s cf-8mhz 3.0v to 5.5v 1/1 375ns 1/16 104.3 s 64.2 s cf-4mhz 3.0v to 5.5v 1/1 750ns 1/8 104.5 s 64.5 s note 6-1: the quantization error (1/2lsb ) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12-bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conve rsion mode is switched from 8-bit to 12-bit conversion mode.
LC87F7J32A no.a0886-20/29 power-on reset (por) characteristics at ta=-40 to +85 c, v ss 1=v ss 2=v ss 3=0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.87v 2.75 2.87 2.99 por release voltage porr ? select from option. (note 7-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 7. (note 7-2) 0.7 0.95 v power supply rise time poris ? power supply rise time from 0v to 2.0v. 100 ms note7-1: the por release level can be selected out of 4 levels only when the lvd reset function is disabled. note7-2: por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta=-40 to +85 c , v ss 1=v ss 2=v ss 3=0v specification parameter symbol pin/remarks conditions option selected voltage min. typ. max. unit 2.31v 2.21 2.31 2.41 2.81v 2.71 2.81 2.91 lvd reset voltage (note 8-2) lvdet 4.28v 4.18 4.28 4.38 v 2.31v 55 2.81v 60 lvd hysteresys width lvhys ? select from option. (note 8-1) (note 8-3) ? see fig. 8. 4.28v 65 mv detection voltage unknown state lvuks ? see fig. 8. (note 8-4) 0.7 0.95 v low voltage dtection minimum width (reply sensitivity) tlvdw ? see fig. 9. 0.2 ms note8-1: the lvd reset level can be selected out of 3 levels only when the lvd reset function is enabled. note8-2: lvd reset voltage specification values do not include hysteresis voltage. note8-3: lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. note8-4: lvd is in an unknown state before transistors start operation.
LC87F7J32A no.a0886-21/29 consumption current characteristics at ta = -40 c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 8.5 23 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 3.6 4.8 13 iddop(3) 4.5 to 5.5 6.9 19 iddop(4) 3.0 to 3.6 3.9 11 iddop(5) ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.5 to 3.0 3.1 8.8 iddop(6) 4.5 to 5.5 2.4 6.6 iddop(7) 3.0 to 3.6 1.3 3.5 iddop(8) ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 1.1 3.2 iddop(9) 4.5 to 5.5 0.7 3.3 iddop(10) 3.0 to 3.6 0.4 1.9 iddop(11) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.3 1.5 iddop(12) 4.5 to 5.5 7.8 21 iddop(13) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz wifh frequency variable rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 4.5 12 iddop(14) 4.5 to 5.5 3.6 10 iddop(15) 3.0 to 3.6 2.8 7.7 iddop(16) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz wifh frequency variable rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 1.8 5.5 ma iddop(17) 4.5 to 5.5 35 120 iddop(18) 3.0 to 3.6 18 72 normal mode consumption current (note 9-1) iddop(19) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 13 53 a iddhalt(1) 4.5 to 5.5 3.8 9.2 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 3.6 2.0 5.0 iddhalt(3) 4.5 to 5.5 2.8 7.7 iddhalt(4) 3.0 to 3.6 1.4 3.9 halt mode consumption current (note 9-1) iddhalt(5) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.5 to 3.0 1.1 3.1 ma note 9-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
LC87F7J32A no.a0886-22/29 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(6) 4.5 to 5.5 1.2 3.3 iddhalt(7) 3.0 to 3.6 0.6 1.7 iddhalt(8) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.4 1.2 iddhalt(9) 4.5 to 5.5 0.40 1.89 iddhalt(10) 3.0 to 3.6 0.20 0.83 iddhalt(11) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.15 0.69 iddhalt(12) 4.5 to 5.5 3.3 9.0 iddhalt(13) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz wifh frequency variable rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 1.6 4.4 iddhalt(14) 4.5 to 5.5 1.7 4.6 iddhalt(15) 3.0 to 3.6 0.8 2.2 iddhalt(16) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz wifh frequency variable rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 0.6 1.7 ma iddhalt(17) 4.5 to 5.5 22 82 iddhalt(18) 3.0 to 3.6 9 33 halt mode consumption current (note 9-1) iddhalt(19) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz cr ystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 6 26 a iddhold(1) 4.5 to 5.5 0.05 22 iddhold(2) 3.0 to 3.6 0.03 13 iddhold(3) ? hold mode ? cf1=vdd or open (external clock mode) 2.2 to 3.0 0.02 9 iddhold(4) 4.5 to 5.5 3.5 25 iddhold(5) 3.0 to 3.6 2.2 15 hold mode consumption current iddhold(6) v dd 1 ? hold mode ? cf1=v dd or open (external clock mode) ? lvd option selected 2.2 to 3.0 2.0 10 iddhold(7) 4.5 to 5.5 19 65 iddhold(8) 3.0 to 3.6 7.0 31 timer hold mode consumption current iddhold(9) v dd 1 ? timer hold mode ? cf1=v dd or open (external clock mode) ? fmx?tal=32.768khz crystal oscillation mode 2.2 to 3.0 4.5 17 a note 9-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. f-rom programming characteristics at ta = +10 c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current included 3.0 to 5.5 5 10 ma ? erasing time 20 30 ms programming time tfw(1) ? programming time 3.0 to 5.5 40 60 s
LC87F7J32A no.a0886-23/29 uart (full duplex) op erating conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer ate ubr utx(s0), urx(s1) 2.2 to 5.5 16/3 8192/3 tcyc data length: 7/8/9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: none example of 8-bit data transmission mode processing (transmit data=55h) example of 8-bit data reception m ode processing (r eceive data=55h) characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0g52-r0 (10) (10) open 470 3.0 to 5.5 0.05 0.15 internal c1, c2 cstce8m00g52-r0 (10) (10) o pen 2.2k 2.7 to 5.5 0.05 0.15 8mhz murata cstls8m00g53-b0 (15) (15) open 680 2.5 to 5.5 0.05 0.15 internal c1, c2 cstcr4m00g53-r0 (15) (15) o pen 3.3k 2.2 to 5.5 0.05 0.15 4mhz murata cstls4m00g53-b0 (15) (15) o pen 3.3k 2.2 to 5.5 0.05 0.15 internal c1, c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit ubr receive data (lsb first) start of reception end of reception start bit stop bit
LC87F7J32A no.a0886-24/29 characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyokomu mc-306 18 18 open 560 2.2 to 5.5 1.4 3.0 applicable cl value= 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
LC87F7J32A no.a0886-25/29 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold release signal valid tmscf tmsx?tal hold halt hold reset signal absent
LC87F7J32A no.a0886-26/29 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC87F7J32A no.a0886-27/29 figure 8 lcd bias resistors figure 9 waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only when power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. vlcd sw: on (vlcd=v dd ) 2/3vlcd 1/2vlcd 1/3vlcd sw : on/off (programmable) v dd gnd rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d v dd res por release voltage (porrl) unknown-state (pouks) (a) (b) reset period reset period 100
LC87F7J32A no.a0886-28/29 figure 10 waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repe titions of reset release and entry cycles near the detection level. figure 11 low voltage detection minimum width (example of momentary power loss/voltage variation waveform) v dd lvd reset voltage tlvdw v ss lvd release voltage lvdet-0.5v v dd res lvd hysteresis width (lvhys) unknown-state (lvuks) reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet) reset period reset period
LC87F7J32A no.a0886-29/29 ps sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. this catalog provides information as of may, 2 007. specifications and info rmation herein are subject to change without notice.

▲Up To Search▲

Price & Availability of LC87F7J32A

	To Download LC87F7J32A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .